Recently, reconfigurable devices, such as an FPGA (Field Programmable Gate Array) and a DRP (Dynamically Reconfigurable Processor), are getting attention. Those devices have characteristics of realizing about the same performance as that of an exclusive logic circuit, and enabling dynamic reconfiguration of a circuit.
For example, Japanese Patent No. 3987782 and Japanese Patent No. 3987783 disclose an example of the architecture of a DRP.
An FPGA and a DRP perform a circuit operation in accordance with a configuration code stored in advance in a configuration memory in those devices.
Therefore, to realize a large-scale circuit, it is necessary to store a large number of configuration codes. In particular, like a DRP, when a plurality of configurations are dynamically changed over a time axis, it is necessary to store a further large number of configuration codes.
However, when the size of a configuration memory increases, the ratio that the configuration memory occupies in a whole computation unit increases, while the ratio of an arithmetic circuit decreases. Accordingly, a distance to the arithmetic circuit of another computation unit (in other words, a distance between computation units) increases, so that a wiring delay may increase.
In order to suppress any increment of the wiring delay, for example, a technique of using a transistor which operates at a fast speed is considerable. However, a transistor which operates at a fast speed generally has a large leak current, resulting in increment of power consumption.